FA-80-12M1H显微镜检查

      1. e2v commends to use E = 1 because of the limited EEPROM write cycles refer on page 12.

      2. Camera gain (dB) = G x 0.047. A and B gain value are set in manufacturing but can be adjust if necessary. 

      3. Commands “H=2” and “H=4” will give 10 and 15 MHz data rate which are not compatible with Camera bbbb standard. Please don’t use it.

      4. The pinout corresponding to this option is fully compatible with the Camera bbbb standard

      5. The test pattern is useful to check if the interfacing is well done. The user should see a jagged image of 256 pixels steps.

      6. The offset is set in manufacturing to balance both the channels. The initial setting is about 8 (~ 130 LSB). In some cases, the user may have to change it (for example if the ambient temperature is very high).

      7. To be used for multi-camera synchronization. Refer to Figure 8

      Synchronization Mode Four different modes may be defined under user control. The TRIG1 and TRIG2 signals may be used to trigger external events and to control the integration time. The Master clock is either external or internal clock. 8.1.1 Free Run Mode with Integration Time Setting The integration and readout periods start automatically and immediabbby after the previous period. The read-out time depends on pixel number and pixel rate. Note: 1. The integration time is set by the serial line and should be higher than the read-out time (otherwise it is adjusted to the readout time). Figure 8-1. Timing Diagram 8.1.2 Triggered Mode with Integration Time Setting The integration period starts immediabbby after the rising edge of TRIG1 bbbbb signal. The Integration time is set by the serial line. This integration period is immediabbby followed by a readout period. The read-out time depends on pixel number and the pixel rate. Table 8-1. Free Run Mode with Integration Time Setting

     Label Debbbbbbion Min Typ Max ti Integration time duration (1) – 13 ms tg Consecutive integration period gap (at maximum frequency) – 6 µs – tt Integration period stop to read-out start delay – 1 µs – 

    Triggered Mode with Integration Time Setting The integration period starts immediabbby after the rising edge of TRIG1 bbbbb signal. The Integration time is set by the serial line. This integration period is immediabbby followed by a readout period. The read-out time depends on pixel number and the pixel rate. Table 8-1. Free Run Mode with Integration Time Setting Label Debbbbbbion Min Typ Max ti Integration time duration (1) – 13 ms tg Consecutive integration period gap (at maximum frequency) – 6 µs – tt Integration period stop to read-out start delay – 1 µs – Integration N Readout N-1 Readout N Integration N+1 tt ti tg Table 8-2. Triggered Mode with Integration Time Setting Label Debbbbbbion Min Typ Max ti Integration time duration 5 µs – 13 ms td TRIG1 rising to integration period start delay – 5.5 µs –